1. Field of the Invention
The present invention is related to a technique for suppressing noise as emitted from semiconductor devices such as integrated circuits, for example, a technique for suppressing EMI noise as emitted from the power supply system of the semiconductor device, noise as originating from the resonance between circuit elements contained in the semiconductor device, and so forth.
2. Description of the Related Art
Recently, emission of EMI noise becomes substantially problematic while the packing densities of integrated circuits have been increased. The EMI noise is thought to be generated in accordance with the mechanism as described in the followings. When a number of circuit elements are turned off/on at the same time within an integrated circuit, instantaneous currents are passed through a power source line. This rapidly changing electric current contains a number of high frequency components. Because of this, the wirings formed within the integrated circuit and the wirings outside of the integrated circuit can function as antennas, from which the high frequency components of said electric current are radiated as electromagnetic waves, i.e., EMI noise.
In order to attenuate EMI noise, capacitors and/or resistors have been inserted into suitable locations of the power system in the prior art technique. Also, the power system has been designed with a plurality of electric power supply systems for the same purpose. However, in the case of the prior art technique, the noise level can be evaluated only by actually fabricating the integrated circuit and measuring the electric current as output from the terminals of the integrated circuit. Accordingly, in order to attenuate the noise level by the prior art technique, actual measurement has to be repeated with a number of variations of the locations and the values of the capacitors and the resistors as inserted.
The reduction of EMI noise can be predicted in advance of manufacturing semiconductor chips if the spectral components of the electric current as generated associated with the operation of the integrated circuit can be analyzed on the basis of the design date. Furthermore, the locations and the values of the capacitors and the resistors as inserted can be optimized in advance of manufacturing semiconductor chips if it is possible to analyze the current flows and the spectral components of the electric current at the respective nodes inside of the integrated circuit in addition to the spectral components of the electric current at the pads of the integrated circuit. It is, however, difficult to analyze the current flows and the spectral components of the electric current at the respective nodes inside of the integrated circuit since the information about the current flows is not available by means of actual measurement.
A simulation system and a method for the semiconductor integrated circuits have been proposed in Japanese Patent Published Application No. Hei 9-55433 as a prior art technique for analyzing the power system of such an integrated circuit by the use of the result of automatic layout. In accordance with the simulation system and method, the voltage drop of the power lines and the ground lines within a circuit can be automatically obtained. Furthermore, an analyzing system and a method for analyzing the power networks of very large-scale integrated circuits have been proposed in Japanese Patent Published Application No. Hei 9-55433 by compacting functional regions of the layout of a semiconductor integrated circuit into compaction component values and simulating the power network on the basis of the compaction component values. In accordance with the simulation system and method, it is possible to conduct an effective analysis of the performance of the power network of a very large-seals integrated circuit. However, these conventional techniques are directed to the analysis of the voltage drop and the electromigration of the power system but not provided for the analysis of the spectral components of the electric currents and the current paths of power supply systems.
On the other hand another simulation method has been proposed in Japanese Patent Published Application NO. Hei 7-175838 in which circuit simulation is conducted by the use of a current source for representing the current/voltage waveforms of the digital circuits contained in a power supply netlist. However, the purpose of the conventional technique is to improve the accuracy of calculation of the noise level of an electric power source by calibrating the generation time of triangular waves. Namely, it is impossible to analyze the spectral components of the electric current in the power system, since the conventional technique is not directed to the measure to reduce EMI noise.
On the other hand, an integrated circuit can be recognized as an LC parallel resonant circuit equivalent thereto so that substantial noise is sometimes generated in the electric power supply system by the resonance in the circuit. The resonance in the circuit serves also to amplify EMI noise. As the measures for reducing noise associated with the electric power supply system, there are thought several methods, for example, by canceling our the resonant waves, reducing the Q of the resonance and so forth.
It in proposed in Japanese Patent Published Application NO. Hei10-23664 to cancel out the resonant waves by inserting an RLC serial resonant circuit in the integrated circuit. However, it is difficult to accurately determine the capacitance and the inductance of the LC circuit in accordance with the technique as proposed. For this reason, in order to determine the respective value of R, L and C to be inserted by the prior art technique, actual measurement nas to be repeated with a number of variations of the respective values, resulting in the problem that it takes much labor time and costs as required.
Furthermore, a resistor may be inserted to the electric power supply system in order to reduce the Q of the resonance. However, in this case, insertion of a large resistor possibly entails an undesirable power voltage drop. Because of this, in order to determine the resistance value of the resistor, actual measurement has to be repeated with a number of variations of the resistance values, resulting in the problem that it takes much lator time and costs as required.